Design and Implementation of a Ternary FIR Filter using Sigma Delta Modulation
نویسندگان
چکیده
This paper describes the design and implementation of a single-bit FIR Filter with balanced ternary coefficients (i.e. -1/0/+1) aimed at general DSP applications. The fixed filter coefficients were computed using a sigma delta modulation technique. The filter is based on a hierarchical adder structure that can be pipelined for high performance that has been designed and simulated in VHDL. The filter structure exhibits low I/O and core area usage and high performance—achieving clock speeds in excess of 350MHz on a low-cost FPGA and over 600MHz on a high-performance device. The filter is intended to support video and audio processing applications in mobile communication systems.
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